`timescale 1ns / 1ps

module uart_tb();
    reg        clock;
    reg        reset;
    reg        write;
    reg  [7:0] data_in;       // tx going into uart, out of serial port
    reg        read;

    wire [7:0] data_out;      // rx coming in from serial port, out of uart
    wire       data_ready;
    wire [8:0] rx_count;      // Number of available bytes

    reg        RxD;                  // Input RxD pin
    wire       TxD;                  // Output TxD pin

    initial begin
      clock = 0;
      reset = 0;

      read = 1;
      RxD = 0;

      # 80;
      reset = 1;
      # 80;
      reset = 0;
    end

    always begin
      # 8 clock = ~clock; //66MHz
    end

    initial begin
      write = 0;
      data_in = 0;
      @(posedge reset);
      @(negedge reset);
      @(posedge clock);
      write = 1;
      data_in = 8'haa;
    end

uart_min U_UART_MIN(
         .clock(clock)
        ,.reset(reset)
        ,.write(write)
        ,.data_in(data_in)
        ,.read(read)
        ,.data_out(data_out)
        ,.data_ready(data_ready)
        ,.rx_count(rx_count)

        ,.RxD(RxD)
        ,.TxD(TxD)
        );

endmodule
